ADC acquisition and DDS clock

otinanai · Joined: 04 Apr 2009 Posts: 6

The ADCs acquire the analog values during the falling or the rising edge of the DDS clock?

Can you pls explain when does the sampling begin and when does it end in reference to the DDS clock?

dmclane · Joined: 31 Mar 2006 Posts: 57

The A/Ds acquire data on the falling edge of the sample timebase (DDS, external clock or timer). All channels sample and convert synchronously.

After a falling edge on the sample clock, the logic waits until the converter indicates that the sample is ready then collects data from all the A/D devices. The samples from the enabled channels are stored into a FIFO in the logic after error compensation. This process takes about 3.8 us. Minimum cycle time on the A/D devices is 4 us.

otinanai · Joined: 04 Apr 2009 Posts: 6

So, the analogue signal is sampled and converted in 3.8usec and the next quickest sampling will start in 4usec.

Now my question is the following:
for how much time after the falling edge of the sample clock must the A/D channel be connected to the sampled signal to ensure that the sampling is done correctly?

I'm asking because we want to connect 2 inputs in each A/D channel through a multiplexer. The multiplexer will change the inputs that are connected to the A/D channel.

If the A/D channel has a sampling frequency of 250kHz and we wish to have 2 inputs that share the A/D (with a sampling frequency of 125kHz each) when is it the best moment to change from one input to the other?
Is it the rising edge of the sample clock?

dmclane · Joined: 31 Mar 2006 Posts: 57

The A/D acquires the signal in 1.8 uS. If you use the rising edge of the sample clock, this would be a good time to switch the signal.

The analog filter on the A/D channel will have to settle as well however to result in accurate conversions. Bandwidth of this filter is ~100 kHz for the standard configuration. This means that the signal will not settle completely before conversion if there are large differences in amplitude between the two multiplexed signals.

This filter can be removed if necessary by removing four capacitors per channel. On channel 0, these are C6, C7, C8, C9.