Timer Selection

Charles Greenlaw · Joined: 21 Oct 2008 Posts: 3

What timer(s) would you suggest I use to accomplish the following on my ChicoPlus with AIX20 module:

1. Generate 500 microsecond positive pulses on a DIO pin at a 10 Hz rate.

2. At the leading edge of this pulse, take 8192 samples from the four ADC channels at 20 MHz.

I presume streaming mode would be best for saving this data to disk.

Thanks,

Charles

gmiller · Joined: 07 Mar 2006 Posts: 105 Location: Simi Valley, CA.

Both Timer 0 and Timer 1 can be based on the DDS timer.
If you design a flow of data to the DIO with the Timer (0, 1) as the output latching control you can send data out the DIO to act as a trigger.

Respectfully Gary

Charles Greenlaw · Joined: 21 Oct 2008 Posts: 3

Due to the terse description of the timers in the Armanda manual, that suggestion didn't help me any. I decided to try a simpler approach, using an external trigger to drive my system. The description of the IIRetrigger component (Pg. 44) suggests that this is the timer to use. I installed it, set the clock rate (DDS) to 20 MHz, FrameCount to 8192 (number of adc samples per trigger), FrameRate to 10 (the approximate rate of external triggers), and the Rate(?) to 20 MHz as well.

Questions:

1. Do I need the IIClock component installed to setup the clock or is IIRetrigger enough?

2. Does the External Trigger Input on the DIO connector trigger the IIRetrigger component? There is no mention of where this trigger arises in the manual that I could find.

3. Where can I observe the gated sample clocks out of the timer? Is there a way to direct it out the DIO connector so I can see it on a scope? I want to KNOW that this pulse train is synchronous with my input gate.

Thanks,

Charles

gmiller · Joined: 07 Mar 2006 Posts: 105 Location: Simi Valley, CA.

#1 you do not need any other clock to use with this. Retrigger is a complete clock.

#2 The External Interrupt pin on the ChicoPlus is the input for the frame start. The signal must be held as long or longer then it takes to take the frame.

#3 There is no place to observe the gated clocks as these are done inside the FPGA. This is then sent to the Omnibus board from there. These clocks do not leave the board in this fashion.

I have done a Retrigger for an A4D1 this could be modified easily for an AIX. Write to me if your interested in this from Borland IDE.

Respectfully Gary

Charles Greenlaw · Joined: 21 Oct 2008 Posts: 3

Gary,

Yes, please. I would like to see an example.

Thanks,

Charles