ADC and DDC channel detail.

Sabeen Zameer · Joined: 12 Feb 2008 Posts: 10

Hi

It is not labelled on the channels within the Snap gui setup tab that which channel ( ch0, ch1 .. ) is associated with which device ( ADC or DDC ) . what we assume is that ch0 - ch3 correspond to ADCs and the rest to the DDC channels.

Kindly correct us if we are wrong !
Looking forward to ur reply.
cheers.

Sabeen

jhenderson · Posted: Thu Sep 18, 2008 5:41 am Post subject: DR channel mapping

Channels 0..3 correspond with the raw A/D device 0..3 outputs. Channels 4..7 correspond to the output from the Greychip 5016 devices 0..3. Note that the output format produced by channels 4..7 may actually contain down-conversion results from up to four tunable channels. In essence, up to four channels may be interleaved within the data produced on PIDs 4..7.

firasmail2000@yahoo.com · Joined: 26 Sep 2007 Posts: 12

Hi,

How we configure the DR card to send only one channel from the available 4 DDC channels that belong to single GC5016?

Regards

Firas

jhenderson · Posted: Thu Sep 18, 2008 1:49 pm Post subject: Graychip data sheet

Consult the GC5016 data sheet for details on configuration of the device to change output format, enable specific DDC channels, etc. We do not have a stock example illustrating that mode of operation.

firas · Joined: 02 Nov 2007 Posts: 17 Location: Jordan

Hi Jim,

I followed your suggestion about disabling specific GC5016 channels and contacted TI Semiconductor Technical Support. They replied with the following:

[" The cic_sync, nco_sync, gain_sync, and fir_sync for the channels to be disabled can be set to 6 or 7"]

I applied their recommendations to my DR GC5016 configuration with no luck. I still receive all channels. Then I tried to set the value of the register 0X1B to 0X0001 to tell the FPGA that only one channel is working but it still streaming all GC5016 channels to me.

It seems FPGA image problem. Is their any recommendations?. Thank you.

Best Regards,

Firas

amane · Posted: Fri Oct 03, 2008 8:40 am Post subject:

Hi,
In Snap example
DDC 0 can accept data from ADC 0
DDC 1 can accept data from ADC 1
DDC 2 can accept data from ADC 2
DDC 3 can accept data from ADC 3

However , even though snap is fixed , user can write their own application software and select any ADC input to any DDC channel.
Please review the framework logic user guide for more details.
The required register settings are described in detail.
Sincerely,
Amit