DigitalI/O port

damiencourousse · Joined: 23 Mar 2006 Posts: 13

Hello,

We would like some explanation concerning the digital outputs on the DSP Toro Baseboard (C67xx), on the JP1 connector (DigitalIo class).

Our main problem is that we cannot control the DigitalI/O port in an interrupt handler function whereas the same code works in the IIMain() function. Please find more explanation below.

We will use the DigitalIO port to control an external peripheral; the whole 32 pins are used in output mode. To set the 32 digital pins to output, the DIO configuration register was set to 0x00FF, according to the user's manual. Then we can write/clear bits independantly or in fields with the DigitalIo::Write/ClearBit() and DigitalIo::Write/ClearField() methods. Is that right ?

The DigitalIO will be controlled by a CLK signal; this should hook an interrupt handler managing the DigitalIO signals.

If we control the DigitalIO port in the IIMain() function, it works fine:

jhenderson · Posted: Thu Jul 19, 2007 10:03 am Post subject: flag mishandled

I suspect that you are encountering some sort of volatility issue with the flag variable in the ISR. The TI compiler is aggressive about optimizing-out such variables and it mat not be generating the code you expect. Try initializing this variable outside of the ISR function as:

damiencourousse · Joined: 23 Mar 2006 Posts: 13

Hello Jim,

Thanks for your prompt feedback,

Yes, we known about the volatile "issue".
Actually I should have made my example clearer.
We have tried the following, without using any flag; and this does not work. Here is an example below:

jhenderson · Posted: Fri Jul 20, 2007 6:21 am Post subject: DIO in ISR

Damien -

Perhaps the problem is more fundamental. Is there any chance that your myDioPtr has not been properly initialized prior to the first invocation of the ISR?

Please tally a volatile variable into this new ISR code to verify that this ISR is still running continuously. Also, note that the code snippet

damiencourousse · Joined: 23 Mar 2006 Posts: 13

Hello,

Concerning this code snipplet:

jhenderson · Posted: Tue Jul 24, 2007 5:00 pm Post subject: Servo base class

The Servo base class was specifically designed to perform all necessary initialization of the Toro timebase and analog I/O, plus hook the native interrupt to allow you to easily implement your own servo.

It is not reasonable to expect that the ISR should run by simply configuring EXT_7 in the CDB to point to a particular handler function. The CDB does not handle the myriad details associated with routing the interrupt source to the DSP interrupt pin, configuring the timebase, etc. I don't know why you are trying to avoid use of the ServoBase class, but if you insist on doing so, you will need to scrutinize the functionality embedded within that class and perform that initialization yourself. This will require careful study of the class implementation and the internal register description documentation.

damiencourousse · Joined: 23 Mar 2006 Posts: 13

Hello Jim,

jhenderson · Posted: Wed Jul 25, 2007 1:31 pm Post subject: External DIO clock

Unfortunately, the External DIO clock cannot be routed by the FPGA to the DSP external interrupts on the Toro design. However, as a possible work-wround, you might consider running a parallel copy of the EXT CLK signal into J2, the External Interrupt Input. The J2 input is included in the matrix of signals that may be programmatically routed to the DSP interrupts 4..7.

See the attachment for some reference code illustrating routing the external interrupt to DSP interrupt 5 to handle an external low-speed interrupt-driven device. Note: Code fragment extracted from existing application. May not compile as-is.