ISE DS 12.1

ywu · Joined: 03 Sep 2009 Posts: 40

Any support of FrameWork Logic on ISE DS 12.1? Thanks,

amane · Posted: Mon May 17, 2010 7:34 am Post subject:

Current ISE version supported for X5 series boards is

ISE 11.3
System Generator 11.3
Matlab 2009a/ 2009b

Sincerely,
Amit Mane
System Engineer
Innovative Integration Inc
Simi Valley,Ca 93065

collins_ · Joined: 12 Oct 2009 Posts: 2 Location: paris

When are you planning to provide support for ISE 12.1 ?
Why i need :
*From xilinx employee : In 12.1 multi-threading will be supported by the router. For both place and route, the 12.1 support will be able to use up to 4 processors. This will be supported on Windows. All of this applies only to the newer architectures (V5,V6,S6).
=> So i'm expecting save time when i need to renew my design...

* I use x5_400m for multi_correlation so i have to physically allocate space for each correlator.The new Planahead is totally refounded, i'm testing it since one week... Very useful!!
But i'm not able to succes in implementatin with planahead :
Pack: 2811 - Directed packing was unable to obey the user design constraints (LOC=SLICE_X91Y45) which requires the combination of the symbols listed below to be packed into a single SLICEL component...
Pack: 2811 - Directed packing was unable to obey the user design constraints (LOC=SLICE_X68Y48) which requires the combination of the symbols listed below to be packed into a single SLICEM component...

I keep looking for new version of x5_400m supporting 12.1...
Thanks.

amane · Posted: Fri May 28, 2010 2:42 pm Post subject:

Hi,
ISE 12.1 does not support Innovative Integration's BSP using Xilinx System Generator (Unknown Compilations errors).

This issue is completely outside Innovative's control.
WE have opened a webcase with Xilinx to resolve this issue asap.
The webcase number with Xilinx is

834724

Since all our X5 series boards use both ISE and System Generator features,
we can upgrade to ISE 12.1 only when this issue is resolved.

Sincerely,
Amit Mane
System Engineer
Innovative Integration Inc
Simi Valley,Ca 93065

collins_ · Joined: 12 Oct 2009 Posts: 2 Location: paris

Thanks for answer.

ywu · Joined: 03 Sep 2009 Posts: 40

When the framework logic is compiled with DS 12.1, it gets this error message:

"LIT:600 - IOBUFDS symbol "inst_ddr2_fifo_mq/ddr2_controller_inst/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u_iob_dqs/gen_dqs_iob_ddr2_ddr3.u_iobuf_dqs" (output signal=inst_ddr2_fifo_mq/ddr2_controller_inst/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u_iob_dqs/dqs_ibuf) does not have IOSTANDARD specified. Map is unable to generate a default IOSTANDARD for IOBUFDS, one has to be explicitly provided."

Any quick fix?

Thanks, regards,

ywu · Joined: 03 Sep 2009 Posts: 40

I still cannot understand the performance out of the DAC on the X5-400M of rev a and c.

No filter and invsinc operation is turned on DAC chipset.

A high quality external clock of 200 MHz is fed into the DAC. I suppose this clock is also fed into the asynfifo in the Virtex-5 chip. I assume the Virtex-5 chip has a 200 MHz system clock independent of the DAC sampling clock. During a free run without asynfifo, both clocks are measured. I noticed that the DAC sampling clock is 3 to 4 kHz faster than the Virtex-5 chip's sysclk since the DAC output is gaining extra sample. I adjusted the DAC sampling clock to 196 MHz so that the DAC sampling clock is definitely slower than the Virtex-5 sysclk. But the signal of the DAC's output starts to degenerate fast.

I'm really afraid of my assumption being wrong; such as Virtex-5 fs clock is not really from the DAC sampling clock.

Any suggestions?

Thanks,