New FrameWork Build?

BrandonJ · Joined: 14 Apr 2006 Posts: 45 Location: Washington, DC

I downloaded and installed all of the new UWB and Malibu updates. I noticed that the FrameWork logic was not updated. There is still an issue with the constraint file improperly reporting timing errors due to the PCI FIFO read/write clocks that I tried to solve myself, but didn't have any success.

Is there any chance of getting an update?

Thanks,
-Brandon

dmclane · Joined: 31 Mar 2006 Posts: 57

The timing errors reported are harmless and can be safely ignored. We plan to issue an update the eliminates the cross-domain timing group ignores in the coming few weeks.

BrandonJ · Joined: 14 Apr 2006 Posts: 45 Location: Washington, DC

Ok great.

Yes, I know they are harmless for the default build, but it inhibits me from modifying the logic and knowing the device will operate correctly without physically testing it (inefficient).

FYI, on page 240 of the FrameWork Logic User Guide I believe Illustration 125 is slightly incorrect for the PMC UWB. It appears the FIFOs are actually 1k with 64-bits in/64-bit out? Just thought I'd mention it...

edziedzic · Joined: 24 May 2006 Posts: 8

We are scheduled to do a new build in several weeks.

Nicolas · Joined: 17 May 2006 Posts: 2 Location: Paris, FRANCE

Hi all,

My customer and I are little confused about section 6.2.4.5 Clocks of the framework user logic guide page 93.

Is the system clock 100 MHz, 125 MHz (illustration 59) or 130 MHz ?

It is mentionned that using one system clock for the all processing is simplier, can it be set at let say :123.8 MHz ??

Thank you for your help.
Best regards,

Nicolas Moreau.

edziedzic · Joined: 24 May 2006 Posts: 8

The board system clock is 100 Mhz. It is then spun-up internally to 125 Mhz using a Xilinx DCM. You can change the DCM M/N factor to change the system clock frequency.

BrandonJ · Joined: 14 Apr 2006 Posts: 45 Location: Washington, DC

This is supported? The 'sys_clk' is drives a few other entities, such as the packetizer, ddr, and zbt ram. Can the clocks for these devices scale as well?

edziedzic · Joined: 24 May 2006 Posts: 8

Yes, within reason. I've successfully pushed the DCM sysclk to ~ 150 Mhz, however we haven't fully tested at that speed...

janaka · Joined: 13 Jun 2006 Posts: 7

Hi ,

That's good to hear. I exactly need to do the same thing. I tried DCM with 3/2 to get 150 MHz. I also changed the sys_clk_in constraint to 100 MHz (default value was 112MHz and created many timing errors in PAR). Althought the implementation was completed with no errors, there are many timing errors in PAR. (No errors on sys_clk though). Just wondering whether they are still harmless because the PAR timing report says the design did not meet timing. Will you be fully testing UWB @150MHz ? That would be very useful.

Thanks,
Janaka