DAC and ADC clk phase and frequency

[kappajacko]

I need to recieve a signal and then transmit the received data.

Since both the ADC and DAC are using the same oscillator, I am assuming that the frequency of all 3 clocks is the same, but the phases will be different w.r.t. on clock.

Is this correct?

I am currently using the DAC clk as the clock that reads the ADC fifos and then writes the DAC fifos. The ADC clks just write their respective fifos.

I am currently seeing a variance of 1 clock cycle when I transmit data out the DAC and then receive it on the ADC.

Is safe to say that variance is coming from the analog portion of the design?

Since, all three clocks are using the same crystal I would think the frequency and the phase should be set on power up and then all three drift together.

[amane]

Hi,
ADC and DAC on X5-400M board run on the same internal/ external clock.
So the frequency of the DAC,ADC clock is the same.
The DAC sample clock available inside the FPGA is a half-rate clock.
e.g. if the DACs run at 400Mhz.. FPGA DAC clock is 200MHz.
Same is also true with ADC.
You will definitely see a phase difference between these clocks which is quite expected since the clocks inside FPGA are derived from ADC and DAC on board.

Variance is definitely coming from the analog portion of the design.
Sincerely,
Amit Mane