jhenderson
Site Admin
Joined: 07 Mar 2006
Posts: 1178
Location: So. Cal. USA
|
 Posted: Thu Apr 02, 2009 8:04 am Post subject: Insure phase coherency |
 |
|
| Quote: | I am using the GC5016 DDCs on the DR board to implement a down-conversion application, but the four DDCs are not operating in a phase synchronous manner.
The board utilizes 4 5016 chips, each has 4 DDC channels. I feed an identical signal to all channels, but I find the I/Q phases differ between the DDC outputs.
How do I insure that the DDC channels of all cores remain phase synchronous - I need all 16 DDC channels on four different devices to remain synchronous?
|
The DR module trigger logic within the FPGA has been designed to drive each GC5016's external sync pin. So, whenever a software or external trigger is generated, this signal is asserted on all DDC devices to insure phase coherency.
However, for this mechanism to work properly, each DDC must be programmed properly to respect its external sync signal. The supplied GC5016_script file contained within the Innovative/DigitalReceiver/Hardware/GC5016 Design Tools/GC5016 Design Tools.zip illustrates proper programming of the 5016 devices in this regard. This script is reiterated below. The comments which reference use of sync mode 2, correspond to the function which enables external sync.
| Code: | ###############################################
# GC5016 DDC mode
# clock rate 69.33e6, real input, interleaved complex output
# one to one bit accurate
# AIn->AOut, BIn->BOut, CIn->COut, Din->DOut
###############################################
##############################
# standard print file items
##############################
print table
print gc101
print hfile
print analysis
print debug
##############################
# setup for 4 channels DDC
##############################
mode ab receive
mode cd receive
##############################
# clock rate of GC5016
##############################
fck 69.33 # sampling frequency
##############################
# startup sync
##############################
sync_mode 2 # external sync mode SIA input used for synchronisation
soB_sync 2
#################################
# channel A setup for DDC
#################################
channel 0
#################################
# IO Interface
# 16 bits A port Real Input
# 16 bits A port Real output
#################################
# full rate, A input port
rin_rate 1
rin_cmplx 0
mix_rcv_sel 0
# I output port A
bits 16
pins 16
###################################
# For independent free run GC5016
# channel syncs are set for oneshot
###################################
# channel decimation sync
cic_sync 2 # one shot
fir_sync 2
freq_sync 2
phase_sync 2
nco_sync 2
dith_sync 2
flush_sync 2
gain_sync 2
coef_sync 2
pwr_mtr_sync 2
sck_sync 2
pwr_mtr_on 1
# refer to AGC settings Note
agc_mode 0 # for WCDMA, UMTS, CDMA2000 signal
agc_cf 3 # crest factor is set as -3dB
agc_tc 1000
agc_freeze 0 # AGC is on
###################################
# decimate by 40
###################################
cic_dec 64
fir_dec 4
###################################
# fir tap file
###################################
fir_cmplx 1
fir_coef GC5016_pfir.taps
###################################
# tuning frequency is 14.44 MHz
###################################
#freq_lsb 0x0
#freq_mid 0x4000
#freq_msb 0x5555 # 48 bits Hex expression for the desired tuning frequency, not for "freq", refer to datasheet p.16
freq -14.44 # freq = - (fck - desired tuning frequency ), negative for DDC
###################################
# DDC output mode, in 4 channel can be real, interleaved IQ, or TDM
# , in split IQ mode, can be parallel complex or TDM
# see GC5016 IO Application note for output modes, and signals
###################################
# output port
bits 16
pins 16
routf_tdm 0 # interleaved IQ output = 0, tdm = 1
splitiq = 0
sck_div 0 # output framestrobe, data at the Ck /(sck_div+1) rate
#################################
# channel B setup for DDC test
#################################
channel 1
copy_channel 0
#B Input port
mix_rcv_sel 1
#################################
# channel C setup for DDC test
#################################
channel 2
copy_channel 0
#C Input port
mix_rcv_sel 2
#################################
# channel D setup for DDC test
#################################
channel 3
copy_channel 0
#D Input port
mix_rcv_sel 3
|
_________________
Jim |
|
